1. Field of the Invention
The present invention relates to an analog-to-digital conversion technique, especially to a successive approximation analog-to-digital conversion technique.
2. Description of Related Art
A successive approximation analog-to-digital converter is operable to do binary search over an analog input signal according to all quantitative levels available to the converter and accordingly generate a digital output signal. Among many kinds of successive approximation analog-to-digital converters, a charge redistribution successive approximation analog-to-digital converter is a common choice. This kind of converter uses a capacitor array to sample an analog input signal, then couples the bottom electrode plates of capacitors in the capacitor array to a predetermined voltage one by one according to the descending order of the capacities of the capacitors in view of an instant feedback comparison result so as to gradually decrease the output voltage of the capacitor array (i.e., the voltage of the electrode plates of the capacitors), afterwards compares the output voltage of the capacitor array with the output voltage of an analog-to-digital converting unit (e.g., another capacitor array) or a constant voltage to generate the mentioned instant comparison result, and generates a digital output signal composed of plural bits from a most significant bit (MSB) to a least significant bit (LSB) according to all of the comparison results.
In light of the above, a charge redistribution successive approximation analog-to-digital converter generates a digital output signal composed of bits from a MSB to a LSB by order through many times of voltage comparison. However, based on the principle of successive approximation analog-to-digital conversion, during the last one or few procedures of voltage comparison, the output voltage of the capacitor array will be less and less; consequently, the output voltage tends to being sensitive to noise, and thus the last one or few voltage comparison results could be unreliable, which means that the value of the LSB or the values of the last few bits could be wrong. In order to solve this problem, some prior art generates a bit (e.g., the LSB or one of the last few bits) according to a majority vote of several comparison results, so as to reduce the weight of noise. However, this kind of prior art consumes too much time for the acquisition of extra comparison results (while a lot of time is consumed in the reset of comparator and the procedure of waiting to be reset), and therefore leads to the decrease of analog-to-digital conversion rate and the increase of power consumption. People who are interested in the prior art may refer to the following documents:    (1) U.S. Pat. No. 8,749,412.    (2) U.S. patent application Ser. No. 14/183,637.    (3) Pieter Harpe, Eugenio Cantatore, Arthur van Roermund, “A 2.2/2.7fJ/conversion-step 10/12b 40 kS/s SAR ADC with Data-Driven Noise Reduction”, ISSCC 2013/SESSION 15/DATA CONVERTER TECHNIQUES/15.2.    (4) Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho, “A 71 dB-SNDR 50 MS/s 4.2 mW CMOS SAR ADC by SNR Enhancement Techniques Utilizing Noise”, ISSCC 2013/SESSION 15/DATA CONVERTER TECHNIQUES/15.3.
In addition to the charge redistribution successive approximation analog-to-digital converter, other kinds of successive approximation analog-to-digital converters have similar problems or other problems. Since these kinds of converters and the problems thereof are known in this field, the details thereof is omitted.